There is a need to remember state of conditions entered or derived in semiconductor devices whenever the devices are on. Typically, non-volatile memory (NVM) devices are used in computing systems to store a state of the computing system when the computing systems are turned off. When the computing systems are turned back on, the state is restored for proper operations. Currently, non-volatile memory latches (NVLs) are used as a data storage device for these computing systems to retain and provide data such as read parameters as well as certain configuration information at power up of the computing system. A typical NVL is a flip-flop used as a temporary storage device controlled by a timing signal, which can store 0 or 1. The NVLs automatically recall the parameters and configuration information at power-up that was previously written into them during testing or manufacturing. This information is generally used to control a circuitry of a semiconductor chip device. NVLs, however, require additional real estate on the silicon in addition to the NVM. Also, testing of the NVLs is non-trivial and special attention is needed to protect the controlling signals at power-up to ensure the recalled data from the NVLs. Thus, it is challenging to design a fool-proof power-up recall of data.
Another method to remember the parameters and other configuration information at power-up of the devices is to read them from non-volatile static random access memory (nvSRAM), which is similar to the NVLs mentioned above. Even another method to recall the parameters is to use off-chip memory which contains these parameters, but it presumes that the values of these parameters can be obtained for each particular chip and supplied on demand at the required time.